The present invention generally relates to an I/O redistribution process for an integrated circuit (IC) chip or wafer level package and more particularly, relates to an I/O redistribution process performed on an IC chip that is integrated with a process of forming passive components such as thin film resistors or thin film capacitors on the chip, and the devices thus formed.
In the fabrication of IC devices, semiconductor chips are frequently attached to other chips or other electronic structures such as a printed circuit board. The attachment of the chip is frequently accomplished by a wire bonding process or a flip chip attachment method. In a wire bonding process, each of a series of I/O bump terminal on a chip that is built on an aluminum bonding pad is sequentially bonded to the connecting pads on a substrate. In a flip chip attachment method, all the I/O bumps on the semiconductor chip are terminated with a solder material. For instance, a frequently used solder material is a lead rich, i.e., 97% lead/3% tin high melting temperature solder alloy. In the bonding process, a semiconductor chip is flipped over with the solder bumps aligned and placed in a reflow furnace to effect all the I/O connections to bonding pads on a substrate.
A major processing advantage that is made possible by the flip chip bonding process is its applicability to very high density I/O connections and its high reliability in the interconnects formed when compared to a wire bonding process. Moreover, the wire bonding process also has limitations in the total number of I/O interconnections that can be made in high performance devices.
A limiting factor for using the flip chip bonding process is the fine pitch bonding pads that are frequently required for wire bonding on modem high density devices. For instance, in a high density memory device, bonding pads that are arranged along the periphery of the device may have a pitch, or spacing, as small as 100 xcexcm. At such narrow spacing, it is difficult and costly to accomplish the bonding process to the pads by using solder bumps in a flip chip bonding technique, taken into consideration that solder bumps in this case are of low profile, making underfill process extremely difficult. Besides, a high density substrate which is very costly is required for flip chip bonding a device with a fine pitch I/O.
In order to bond high density IC devices that have peripheral I/O bonding pads with small pitch, i.e., in the range of approximately 100 xcexcm, an I/O redistribution process must first be carried out before the formation of the solder bumps. In an I/O redistribution process, the peripheral I/O bonding pads are redistributed by connective traces to area array I/O bonding pads. This is shown in FIG. 1.
As shown in FIG. 1, IC chip 10 that is equipped with peripheral I/O bonding pads 12 which have a pitch X between the pads as small as 100 xcexcm. Through an I/O redistribution process, a multiplicity of connective traces 14 are formed to redistribute the peripheral bonding pads 12 to area array bonding pads 16. It should be noted that the pitch between the area array bonding pads 16 are greatly increased, i.e., to the extent of approximately three times the pitch between the peripheral bonding pads 12 in this example. The significantly larger pitch between the area array bonding pads 16 allows flip chip bonding to be connected on a low cost substrate manufactured by traditional process. The I/O redistribution process used on modem high density IC devices is therefore an important fabrication step to first enable the device to be solder bumped and then bonded to another chip or to a printed circuit board in a flip chip bonding process. The formation of the connective traces 14 between the various pairs of bonding pads enables the I/O redistribution process to be accomplished. On a module or system, passive components are always included to improve the electrical performance.
It is therefore an object of the present invention to provide an integrated process for I/O redistribution and for forming thin film passive components such as resistors and capacitors simultaneously during the redistribution process encountered in flip chip bumping and wafer level package.
It is a further object of the present invention to provide an integrated process for I/O redistribution and simultaneously forming thin film resistors and capacitors on the connective traces between the bonding pads.
It is another further object of the present invention to provide an integrated process for I/O redistribution and passive components fabrication by utilizing an adhesion layer deposited of a high resistance material for forming the passive components.
It is yet another object of the present invention to provide an integrated process for I/O redistribution and passive components fabrication by utilizing an adhesion layer deposited between the connective traces of a material such as TiW, TiN or any other high resistance materials.
It is still another object of the present invention to provide an integrated process for I/O redistribution and passive components fabrication by utilizing an adhesion layer that is deposited of a high resistance material by a sputtering technique to a thickness between 100 A and 5000 A
It is still another further object of the present invention to provide an integrated circuit device that has bonding pads formed in an I/O redistribution process that includes a high resistance material layer deposited between connective traces and functions as a passive resistor.
It is yet another further object of the present invention to provide an integrated circuit device that has bonding pads formed in an I/O redistribution process which includes a bottom electrode, a dielectric and a top electrode forming a passive capacitor on the connective traces.
In accordance with the present invention, an integrated process for I/O redistribution and passive components fabrication is provided. In the process described below, thin film resistors are fabricated during the I/O redistribution process, and two photolithographic steps are involved. The first photolithographic step is used to relocate the bonding pads, for example, from peripheral to area array configuration. The second photolithographic step is used to form thin film resistors on the connective traces connecting original bonding pads and relocated bonding pads.
In a preferred embodiment, an integrated I/O redistribution and passive components fabrication process can be carried out by the steps of first providing an IC wafer that can be made out of silicon or other semiconducting materials, depositing an adhesion layer on top of the bonding pads and the passivation layer, depositing a conductive layer on top of the adhesion layer, coating a first photoresist layer on the conductive layer, then patterning and etching to define relocated bonding pads and connective traces contacting and connecting original bonding pads and relocated bonding pads. The process is then followed by coating a second photoresist layer, patterning to expose only those segments of connective traces which are then formed into thin film resistors by etching away the top conductive layer and exposing the adhesion layer below. A passivation layer is then deposited on the wafer, and patterned to expose the relocated bonding pads. The wafer is now ready for solder bumping, or any other packaging process.
The adhesion layer utilized can be deposited of a material selected from the group consisting of TiW, TiN, Ti, Cr, NiCr, NiV, Ta2N, W2N, TaAl, TaTi, TaSi and polysilicon. The layer can be deposited by a sputtering technique to a thickness of between about 100 A and about 5000 A. The conductive layer can be deposited of Cu or any other highly conductive metal. The etching process for removing the adhesion layer and the conductive layer can be a wet or dry etch process. The method may further include the step of, after etching away part of the conductive layer between the I/O pads, patterning and etching the adhesion layer such that a passive resistor of a predetermined width and shape can be formed. One of such predetermined shape for achieving high resistivity is a serpentine shape.
The present invention is further directed to an integrated circuit (IC) device that has bonding pads needed to be redistributed by an I/O redistribution process which includes a multiplicity of bonding pads formed on a top surface of the device, at least two connective traces formed of a conductive metal contacting and connecting between at least two pairs of the multiplicity of bonding pads, and a high resistance material layer deposited on top of the IC device providing electrical communication between the at least two connective traces. The device may further include bonding pads formed in an area array. The at least two connective traces each connecting between a peripheral I/O pad and an area array I/O pad. The at least two connective traces can be formed of aluminum or copper or any other high electrical conductivity metal. The at least two connective traces may also be formed over at least two bonding pads that are made of substantially aluminum. The at least two connective traces are formed over at least two bonding pads with an adhesion layer and a conductive layer thereinbetween. The adhesion layer can be formed of a high resistance material for use as a passive resistor. The device further includes a layer of dielectric material embedding the multiplicity of bonding pads for providing electrical insulation thereinbetween. The high resistance material layer can be deposited on top of the dielectric material layer for forming the passive resistor.
In an alternate embodiment, the present invention provides an integrated process for I/O redistribution and passive capacitors fabrication that includes the steps of first providing a substrate that has at least two bonding pads formed thereon, then forming a first dielectric layer covering the at least two bonding pads and providing electrical insulation thereinbetween, forming contact windows on the at least two bonding pads exposing the conductive material, depositing an adhesion layer on top of the at least two bonding pads and the passivation layer, depositing a conductive layer on top of the adhesion layer, coating a first photoresist layer on the conductive layer and patterning to expose areas for forming a connective trace between the at least two bonding pads, depositing a first layer of a conductive metal and forming the connective trace, removing the first photoresist layer, coating a second photoresist layer covering an area between the connective traces, etching away the adhesion layer and the conductive layer from areas not covered by the connective traces and by the second photoresist layer, removing the second photoresist layer, conformally depositing and patterning a second dielectric layer substantially covering the first layer of conductive metal and leaving a contact region uncovered, conformally depositing and patterning a second layer of a conductive metal on top of the second dielectric layer insulated from the first layer of conductive metal, and providing electrical contacts to the contact region of the first layer of conductive metal and to the second layer of conductive metal. The adhesion layer is normally deposited of a high resistance material similar to that utilized in the preferred embodiment. The first and second layer of conductive metal can be deposited of copper or any other high conductivity metals. The first layer of conductive metal can be patterned into a bottom electrode, while the second layer of conductive metal can be patterned into a top electrode for the passive capacitor.